Hello, I have some ideas for skipping TCP in a high level application, but first things first - right now I just want to take the Ethernet core and connect it to a regular PC. I have the following Altera FPGA: http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html It's my understanding that a PHY chip is needed that ultimately interfaces with a female RJ-45 connector. I'm guessing that the "wishbone" interface from the Ethernet core will ultimately be wired to a male PCI interface? Conceptually how does this work? I tried to read the wikipedia entry on wishbone and it sounds like greek to me (my background is VHDL and then higher level languages). I also read somewhere that the Altera's Avalon bus can be used? At first I thought this was going to be easy.. I though I could just wire 32 of the FPGA's output pins to the 32 PCI pins.. wishful thinking :) -- Best, Robert Peterson [cell] 512.825.5309 [facebook] http://www.facebook.com/profile.php?id=674727591 [work blog] http://juzzam.org -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/ethmac/attachments/20081019/7165c77b/attachment.html

In my opinion, wishbone can't connect with the pci interface.First you should use a pci controler such as PLX9052 or PLX9054 to transmite the pci signals to local bus signals.
Second you may design some logic control to connect the local bus with the wishbone.
I am a freshman for studying the mac core.if i had some mistake, plz forgive me.